Verilog for FPGA Design

Duration

2 days

Course Outline

Topic 1: Module1 Introduction to FPGA and CAD Flow

Topic 2: Introduction to Verilog for FPGA design

• Levels of Abstraction, Syntax & Semantics, Reserved Keywords, Ports declaration, Data types, Operators, Relational/Equality/Concatenation/Replication/Conditional, Modeling, Data Flow, Behavioral, Structural, timing control, conditional statements, Process statement / Sensitivity List, State machine (Mealy, Moore), Steps of simulation / Simulation Deltas, Test bench, synthesis

Lab Activities

• Design Entry
• Writing Verilog code
• Test bench
• Simulating Verilog code
• Synthesize the code
• Programming to FPGA board (subject to availability of the board)

Programme scope, delivery arrangements and suitability are confirmed during enquiry.