SystemVerilog for Verification

Duration

4 days

Overview

This intensive, practical course is intended for Verification Engineers interested in the latest verification enhancements to SystemVerilog. While many engineers may have extensive verification experience this course will introduce best-practice usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage.

Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

Objectives

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

• Simulate circuits with Questa / ModelSim.
• Learn and use Verilog/SystemVerilog constructs for simulation and verification.
• Design tester components such as stimuli / test vector generators, transaction monitors, response checkers, and scoreboards.
• Design testbench components using techniques such as simple assertions and file I/O.
• Design testbenches leveraging the use of several UVM facilities.
• Have an overview of advanced techniques such as transaction-level modelling (TLM), bus functional modelling (BFM), temporal assertions-based verification (ABV), constrained random verification (CRV), and functional coverage.

Pre-requisite

This training is targeted for Verification Engineers interested in SystemVerilog for Verification. Attendees should be familiar with verilog 1995.

Introduction

• IC/FPGA design and verification flow.
• The Design Under Verification (DUV).
• Overview of testbench components.
• SystemVerilog Interfaces (SVI)
• Concept of interfaces and modports.
• Interconnecting design or testbench units using SVI.
• Stimuli vector generator design
• Concept of test vector generation, types of stimuli (directed, pseudorandom).
• Unconstrained vs. constrained randomisation.
• Unconstrained randomisation of stimuli.
• Hands-on Practical 1: Unconstrained random stimuli vector generator design and simulation.
• File I/O (input only).
• Hands-on Practical 2: Reading stimuli from a file.
• Transaction monitor design
• Concept of transaction monitoring.
• Simple (non-temporal) assertions-based verification (ABV).
• Hands-on Practical 3: Transaction monitor design using non-temporal assertions.
• Response checker design
• Concept of response checking.
• Scoreboards.
• Hands-on Practical 4: Response checker design using scoreboards logged to simulator’s console.
• File I/O (output only).
• Hands-on Practical 5: Response checker design using scoreboards logged to a file.
• Selected topics in advanced testbench design
• Temporal assertions-based verification (ABV) with SVA / PSL.
• Constrained random verification (CRV).
• Functional coverage.
• Transaction-level modelling (TLM) and bus functional modelling (BFM).

Programme scope, delivery arrangements and suitability are confirmed during enquiry.