Duration
2 days
Description
This course covers the concepts and methodologies established for verification of digital designs, based on the language of System Verilog that has evolved as a standard language for verification and testbench design. SystemVerilog is a superset of Verilog hardware description language (HDL) with both design and verification features. It is widely used in verification environment based on a constrained random layered test bench.
This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify a design under test (DUT) utilizing the new constructs available in SystemVerilog. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this two-day course, you will gain valuable hands-on experience. Participants with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.
Course Objective
This course aims to prepare the participants for industries to take verification tasks. Participants will learn the basic and advanced test bench skills required to drive the desired output. The participants will be able to learn different approaches and techniques for verification. In addition, participants will learn efficient coding styles along with exercises to gain in-depth insight of SystemVerilog features.
Target Audience
This course is for digital design, hardware and verification engineers who will be designing with Verilog and SystemVerilog.
Pre-requisite
This course assumes that engineers have a practical working knowledge of digital design engineering that includes Verilog HDL or have completed Verilog HDL training.
Course Content
Introduction to System Verilog for verification
Basic test bench in System Verilog
Data types
Tasks and functions
SystemVerilog verification building blocks
Constrained Random Verification
Functional Coverage
SystemVerilog Assertions
Programme scope, delivery arrangements and suitability are confirmed during enquiry.