Duration
3 days
Overview
Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture. With the advent of digital HDL, complex features can be implemented in ASIC and SoC, greatly enhancing digital systems and reducing overall system cost. These complex systems require complicated testbenches to verify them. And SystemVerilog is widely used to implement testbenches for verification.
This course introduces the design and implementation of testbenches for simulating and verifying digital systems.
Objectives
This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
- Simulate System Verilog with Questa / ModelSim.
- Understand SVI and testbenches
- Using assertions in testbenches for verification
- Learn and use SystemVerilog constructs for simulation and verification.
Pre-requisite
Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesizable digital systems or simulation testbenches.
Introduction
- IC/FPGA design and verification flow.
- The Design Under Verification (DUV).
- Introduction To System Verilog Testbench simulation using Questa/Modelsim
- Overview of testbench components.
- Basic of OOP
- SystemVerilog vs. Verilog
- What’s new?
- Port declarations
- New datatypes
- Basics of SystemVerilog Interfaces (SVI)
- Concept of interfaces and modports.
- Interconnecting design or testbench units using SVI.
- Threads and concurrency
- Stimuli Randomization
- Constraint Random Verification
- SystemVerilog Assertions
- Immediate assertions
- Concurrent assertions
- Properties and sequences
- Response checking
- Scoreboards
- Checker design
- Functional coverage
- Verification environment
- Overview of advanced testbench techniques
- AVM
- PSL & SVA in complex assertions
- TLM
- BFM
- Functional coverage
- Coverage driven randomization
Programme scope, delivery arrangements and suitability are confirmed during enquiry.