EIEIOTECHNOVATION
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EIEIO / AUTOMATION & EMERGING TECHNOLOGY

Introduction to Integrated Circuit Design with Hands-on Lab

Course outline

3 days

Duration

3 days

Overview

Introduction to Digital ASIC front end and back end design;

Introduction to custom Analog IC design

Learning Outcomes

Upon completion, participants should be able to demonstrate/understand each of the following:

  • Digital ASIC design flow and EDA tools involved
  • Digital Place & Route concepts and EDA tools involved
  • Analog schematic and simulation concepts and EDA tools

Methodology

This Course will utilize a combination of lecture, discussions ,practice session and group discussion including :

  • Instructor Led Classroom training
  • Hands-on labs to help participants build their knowledge and apply the concepts being discussed

Target Audience

Integrated Circuit Engineers & Executives, Design Managers, Modeling Staff, Fabrication & Testing Engineers

Pre-requisite

At least a Bachelor’s degree in Electronic / Computer Engineering

System Requirement

All participants are required to bring their own laptop computers (Windows or Linux) with minimum hardware specification: 64 bits and 6G RAM.

Connection to server provided using VNC

Day 1:

  • Overview of Digital Design Flow
  • Coding with Verilog
  • Design Verification
  • Testbench Writing
  • Simulation with Modelsim
  • Introduction to Synthesis
  • Setup, Libraries and Objects
  • Coding for Synthesis
  • Timing and Area
  • Environmental Attributes
  • Timing Analysis

Day 2:

  • Overview of Physical Design Flow
  • Set-up Environment
  • Reference Library and Milkyway Database
  • Design and Timing set – up
  • Floorplan and Constraints
  • Initial Virtual Flat Placement
  • Analyze Congestion
  • Power Planning
  • Power Network Synthesis
  • Verify PG Connection
  • Place & Route
  • Clock Tree Synthesis
  • Clock Route
  • Global and Detail Routing
  • Search and Repair
  • Verify PG Connection
  • Design for Manufacturing
  • Design Finishing
  • Verify Design Rule Check (DRC)
  • Verify Layout vs Schematic
  • Write –out Netlist and GDS
  • Introduction to Design For Verification (Sign-off)

Day 3:

  • Introduction to Analog Design
  • CMOS Analog Circuits and Design Methodologies
  • Introduction to Analog Circuit Simulator & Simulation
  • Hands-on Analog Circuit design (lab.)
  • Schematic entry and Simulation

Programme scope, delivery arrangements and suitability are confirmed during enquiry.