Duration
3 days
Overview
This three days course introduces the attendee to Verilog Hardware Description Language and its usage for behavioral, structural and RTL coding. The content of this course is combined with many labs to provide hands-on experience to enhance the efficiency of the course. The course begins with basic design flow that uses verilog to usage of the verilog language for design.
Objectives
At the end of this course, the attendees will be able to:
- Understand verilog design flow
- Basic understanding of verilog coding
- Writing verilog RTL coding
- Writing behavioral verilog coding
- Writing testbenches to verify verilog designs
Pre-requisite
Basic design knowledge is preferable but not necessary. This course is targeted for designers, test engineers, programmers, system architects working on ASIC, FPGA and SOC
Course Outline
- Design Flow and methodology
- Difference between prelayout and post layout in design flow
- Verilog and VHDL
- HDL for synthesis
- Behavioral HDL
- Structural HDL
- What is RTL?
- Module and interface declaration
- Basic verilog data types, numbers, strengths
- Verilog operators
- Creating first Verilog file and testbench
- Compiling and simulating Verilog file and testbench
- Using Verilog operators
- Concurrency and sequential
- If-else
- Latch inference
- Boolean logic in RTL
- Case statement and latch inference
- Coding rules to remember
- Blocking and non blocking
- Building design functionality using combinational logic
- Building design functionality using flops and latches
- Inference
- Clocks, resets
- Writing basic testbenches for verification
- Basic synthesis
- Graphical Verilog Design Entry
- Designing and verification of a state machine / controller
- Specification
- Architectural specification
- RTL Coding
- Writing testbench to verify functionality
- Verify all functionality of the RTL code
- Intensive handson with 19 labs
Programme scope, delivery arrangements and suitability are confirmed during enquiry.