Duration
Fundamentals of RISC Processor Architecture
2 days
Overview
The digital age heralds the need for vast data processing and number crunching capabilities to satisfy our insatiable needs. Applications such as video compression/ decompression, voice recognition and 3D graphics typically required electronic devices to incorporate some form of hardware acceleration to produce the required processing throughput.
This course covers the essential concepts of RISC processing such as the instruction set, ALU, registers, Control Unit, data transfers and branching operations.
Course highlight
Participants will have practical design experience using the Altera DE2 FPGA
development board, together with the use of Altera’s Quartus II development software.
They will, at the end of the course, complete a RISC processor.
What You Will Learn
This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
- Understand the fundamentals of RISC processor architectures
- Understand the relationship between programs, machine code and the hardware
- Implement arithmetic and logical functions in hardware
- Develop a simple RISC processor
Who Should Attend
This course is particularly suited for engineers involved in the design of processors or processing cores to achieve high processing speeds.
Prerequisites
Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must have the knowledge of developing synthesizable hardware in Verilog, and have an understanding of algorithmic state machines (ASM).
Course Methodology
This course is presented in a workshop style with lectures interlaced with demonstrations and hands-on practicals for maximum understanding.
Introduction
- Overview of processing
- Harvard vs Von Neumann
- CISC vs RISC
Introduction to MIPS
- The MIPS architecture
- Instruction Set Architecture (subset)
Core MIPS
- Registers
- Register file access
- Hands-on practical: Implementing the Register File
- Adders, subtractors and multipliers
- Logical and comparison operations
- Shift and rotate operations
- Hands-on practical: Developing the ALU
Executing Instructions
- Instruction cycle
- Control Unit
- Hands-on practical: Processor Control
Memory Access
- Data operations
- Data transfer
- Hands-on practical: Memory Access
Branching
- Relative and absolute jumps
- Conditional branching
- Hands-on practical: Program Branching
Programme scope, delivery arrangements and suitability are confirmed during enquiry.