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EIEIO / AUTOMATION & EMERGING TECHNOLOGY

Fundamentals of DSP

Course outline

3 days

Duration

Fundamentals of DSP

3 days

Overview

Digital signal processing (DSP) is the backbone of numerous technological fields, such as wired and wireless communication, military and intelligence gathering, industrial process control, medical science, cryptography and transportation. DSP algorithms such as spectral analysis and Kalman filtering — traditionally executed with specialised digital signal processors — are now increasingly carried out with FPGAs for their greater processing capabilities, increased chip-level integration and lower power consumption. The move towards FPGAs also mean DSP algorithms are now coded in hardware description languages rather than assembly, C or C++.

This course concentrates on the implementation of DSP techniques natively in hardware using Verilog. Participants would be introduced to floating point arithmetic in hardware, DSP hardware patterns, followed by parallelism and pipelining optimisation techniques for implementing high speed and/or low power/footprint digital systems.

Course highlight

Participants will have practical design experience using Quartus II and the Altera DE2 development board.

What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

  • Understand the relationship between software coding and hardware implementation
  • Convert software code to synthesizable hardware
  • Gain and understanding of digital signal processing concepts
  • Understand hardware representation of different numeric types
  • Implement DSP algorithms on FPGAs with Verilog
  • Maximising computation speed through parallelism and pipelining

Who Should Attend

This course is particularly suited for engineers involved in DSP using Verilog.

Prerequisites

Participants should have a degree in electronics (and related) engineering with an understanding of digital systems and FPGA implementation with Verilog.

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Introduction

  • Brief overview of digital signal processing
  • Number storage and representation formats
  • Overview of DSP theory

Algorithmic State Machine

  • Register Transfer Level notation
  • Overview of ASM
  • Hands-on practical: Developing ASMs

FIR filer synthesis

  • Representing filters with block diagrams
  • From block diagrams to hardware
  • Shift registers, multipliers and adders
  • Developing the control unit
  • Hands-on Practical: Synthesis of an FIR Filter

Optimising for speed

  • Overview of pipelining
  • Pipelining the datapath
  • Hands-on Practical: Pipelined FIR Filter

Implementing an IIR filter

  • Overview of IIR filters
  • Hands-on Practical: Implementing Optimised IIR Filters

Programme scope, delivery arrangements and suitability are confirmed during enquiry.