Duration
Digital System Design for Communication and Signal Processing
3 days
Overview
Digital signal processing (DSP) is vital for many fields such as communication, control, imaging, vision and cryptography. This course introduce the concepts and techniques of implementing DSP algorithms in FPGAs, which are vital for real-time computationally intense processing. In addition, this course covers various optimisation techniques that are implemented during the course
Course highlights
Participants will have practical design experience using industry-standard hardware and software tools such as the Altera DE2 development kit and the Quartus II FPGA development environment.
What You Will Learn
This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
- Gain and understanding of digital signal processing concepts
- Understand hardware representation of different numeric types
- Describe algorithms with ASMs
- Implement ASM in hardware
Who Should Attend
This course is particularly suited for engineers involved in DSP development interested in using the HDL digital design and verification flow.
Prerequisites
Participants must have a degree in electronics (or related) engineering with a good
understanding of digital systems and a working knowledge of Verilog.
Course Methodology
This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.
Introduction
- Introduction to FPGAs
- Overview of DSP theory
- Why FPGAs are most suited for DSP?
- Overview of the FPGA design flow
- Hands-on practical: Introduction to the FPGA Design Flow
Basic Verilog 1
- Language constructs
- Data types and representation
- Component instantiation
- Concurrent statements
- Operators
- Hands-on Practical: Combinational Logic
- Concatenation
- Aggregates and array slices
- Enumeration
- Hands-on Practical: Seven Segment Decoder
Basic Verilog 2
- Registers
- Sequential statements
- Blocking assignments
- Counters
- Hands-on Practical: Shift Register
Algorithmic State Machine
- Register Transfer Level notation
- Overview of ASM
- Hands-on practical: Developing ASMs
Implementing the datapath
- Control unit design
- Hands-on practical: ASM to FPGA
- Digital filter synthesis
- FIR filter design
- IIR filter design
- Hands-on Practical: FIR Filter Implementation
Project: IIR Filter
Programme scope, delivery arrangements and suitability are confirmed during enquiry.